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Verification Survey

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What is the size/complexity of your current design (in # of gates)?
< 500k gates
500k-1M gates
1M-2M gates
2M-5M gates
5M-10M gates
10M-20M gates
> 20M gates
What is the size/complexity of your next design (in # of gates)?
< 500k gates
500k-1M gates
1M-2M gates
2M-5M gates
5M-10M gates
10M-20M gates
> 20M gates
How many asynchronous clock domain(s) do you have on your current chip?
1 clock
2 clocks
2-5 clocks
5-10 clocks
10-20 clocks
> 20 clocks
How many asynchronous clock domain(s) do you expect to have on your next chip?
1 clock
2 clocks
2-5 clocks
5-10 clocks
10-20 clocks
> 20 clocks
How many independent power domain(s) do you have on your current chip?
1 power domain
2 power domains
2-5 power domains
> 5 power domains
How many independent power domain(s) do you expect to have on your next chip?
1 power domain
2 power domains
2-5 power domains
> 5 power domains
Select languages you use in your current project:
VHDL
Verilog
SystemVerilog
SystemC
PSL
SVA
OVL
Other:
Select languages you intend to use in your next project:
VHDL
Verilog
SystemVerilog
SystemC
PSL
SVA
OVL
Other:
Do you use the following in your current design? Check all that apply:
Mentor's open source AVM
Constrained random verification
Coverage-based random verification
Clock domain crossing verification
Formal verification/property checking
Low Power verification
Do you intend to use the following in your next design? Check all that apply:
Mentor's open source AVM
Constrained random verification
Coverage-based random verification
Clock domain crossing verification
Formal verification/property checking
Low Power verification

    

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